The present invention relates to a buffer circuit using an IIL (integrated injection logic) gate.
An IIL gate has been developed in recent years as a bipolar element which can be highly integrated. FIG. 1 shows a circuit diagram of the conventional buffer circuit using an IIL gate. The output of the IIL gate 10 is supplied to the output terminal OUT through an output circuit including NPN transistors 12 and 14. That is, the output terminal of the IIL gate 10 is connected to the base of the transistor 12 which has its emitter connected to the base of the transistor 14. The emitter of the transistor 12 is grounded through a resistor 16, while the emitter of the transistor 14 is directly grounded. The collector of the transistor 14 is connected to the output terminal OUT. The base and the collector of the transistor 12 are connected to a power source VCC respectively through resistors 18 and 20.
In the buffer circuit as described above, when the input terminal IN of the IIL gate 10 is at logic "1" level, the logic level of the output terminal of the IIL gate 10 becomes "0", and the transistor 12 is turned off, the logic level at the output terminal OUT being made "1". Contrary to this, if the input terminal IN is at logic "0" level, the transistors 12 and 14 are turned on and the output terminal is at logic "0" level. Thus, the input level appears at the output terminal OUT so that this circuit operates as a buffer circuit.
The power source VCC is ordinarily low (5 through 12 V), however, the output terminal OUT can be impressed by a higher voltage than the power source VCC since OUT is an open collector output. The voltage capable of being impressed upon the output terminal OUT is determined by the breakdown voltage between the collector and the emitter of the transistor 14. Therefore, it is necessary to make the breakdown voltage of the transistor 14 higher than usual. The breakdown voltage of the transistor 14 is determined by V.sub.CER (the collector voltage of the transistor, wherein the emitter is grounded and connected to the base through a resistor). The V.sub.CER is affected by the current amplification factor and the resistance between the base and the emitter, and comes down to V.sub.CEO (the collector voltage in a case in which the emitter is grounded and the base is open) at the worst making it difficult to control. Further, when the buffer circuit is integrated on a chip, it is necessary to increase the impurity density of the epitaxial layer and make the thickness of it thin for increasing the operation speed of the IIL gate and fan-out. On the contrary, this reduces V.sub.CER of the transistor 14. Therefore, in the conventional buffer circuit using the IIL gate, it becomes necessary to reduce the integration density and the operation speed of the IIL gate for increasing the breakdown voltage of the output bipolar transistor.